ESD PROTECTION

In addition to its filtering function, the EMIF02-600FU7 is particularly optimized to perform ESD protection.

ESD protection is based on voltage clamping which can be calculated by :

This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and

then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output

To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical

formulas:

Vin

=

Rg.Vbr

+Rd.Vg

Rg

Vout

=

R.Vbr

+Rd.Vin

R

Vin = 20.33 V

Vout = 7.01 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this

approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at

the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.

The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Vout stage

Fig A3 : ESD clamping behavior

ESD

Surge

Vin

Vout

Rload

S1

S2

Rg

R

Rd

Rd

Vbr

Vbr

Vg

Device to be protected

EMIF02-600FU7

Fig A4 : Measurement conditions

GND

LOW-PASS FILTER

Vin

Vout

GND

GND

EMIF02-600FU7

4/9