OPA171AIDBVT datasheet(22/58 Pages) TI2

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Another common question involves what happens to the amplifier if an input signal is applied to the input when

the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V,

or at a level below the input signal amplitude. If the supplies appear to be high-impedance, then the input

source supplies the operational amplifier current through the current-steering diodes. This state is not a normal

bias condition. Most likely, the amplifier does not operate normally. If the supplies are low-impedance, then the

current through the steering diodes can be quite high. The current level depends on the ability of the input

source to deliver current and any resistance in the input path.

If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the

supply pins; see Figure 7-1. Select the Zener voltage so that the diode does not turn on during normal operation.

However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise

above the safe operating, supply-voltage level.

The OPAx171 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure

7-1. In most circuit applications, the input protection circuitry does not affect the application. However, in low

gain or G = 1 circuits, fast-ramping input signals can forward bias these diodes because the output of the

amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this

forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently

limited, an input series resistor can be used to limit the input signal current. This input series resistor degrades

the low noise performance of the OPAx171. Figure 7-1 shows an example configuration that implements a

current-limiting feedback resistor.

7.2 Typical Application

LOAD

OUT

ISO

Figure 7-2. Unity-Gain Buffer With RISO Stability Compensation

7.2.1 Design Requirements

The design requirements are:

• Supply voltage: 30 V (±15 V)

• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF

• Phase margin: 45° and 60°

7.2.2 Detailed Design Procedure

Figure 7-3 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the

circuit in Figure 7-3. Not shown in Figure 7-3 is the open-loop output resistance of the operational amplifier, Ro.

LOAD

ISO

LOAD

1 + C

× R

× s

T(s) =

1 + R + R

× C

× s

(1)

The transfer function in Equation 1 contains a pole and a zero. The frequency of the pole (fp) is determined by

(Ro + RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). Select RISO such

that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB/decade to obtain a stable

system. Figure 7-3 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.

OPA171, OPA2171, OPA4171

SBOS516H – SEPTEMBER 2010 – REVISED JUNE 2024

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