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OPA2180IDRG4 Datasheet(PDF) 22 Page - Texas Instruments

Part # OPA2180IDRG4
Description  OPAx180 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers
PDF  49 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

OPA2180IDRG4 Datasheet(HTML) 22 Page - Texas Instruments

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OPA180, OPA2180, OPA4180
SBOS584E – NOVEMBER 2011 – REVISED JUNE 2018
www.ti.com
Product Folder Links: OPA180 OPA2180 OPA4180
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Copyright © 2011–2018, Texas Instruments Incorporated
Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
9.2.1.2.1
Component Selection
DAC: For convenience, devices with an external reference option or devices with accessible internal references
are desirable in this application because the reference creates an offset. The DAC selection in this design must
primarily be based on DC error contributions typically described by offset error, gain error, and integral
nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the
DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require
additional consideration.
Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier
is a typical data sheet specification, but in-circuit performance is also affected by drift over temperature, the
common-mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR); thus consideration should be
given to these parameters as well. For ac operation, additional considerations should be made concerning slew
rate and settling time. Input bias current (IIB) can also be a factor, but typically the resistor network is
implemented with sufficiently small resistor values that the effects of input bias current are negligible.
Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components
with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint
may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and
gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details.
The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.
9.2.1.3 Application Curves
Figure 31. Full-Scale Output Waveform



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