PCA9539DGVR datasheet(21/48 Pages) TI2

21 / 48 page

8.3.2.3 Register Descriptions

The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether

the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to

these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the

Input Port register will be accessed next.

Table 8-4. Registers 0 And 1 (Input Port Registers)

Bit

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Default

Bit

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Default

The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

Table 8-5. Registers 2 And 3 (Output Port Registers)

Bit

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Default

Bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Default

The Polarity Inversion registers (registers 4 and 5) allow Polarity Inversion of pins defined as inputs by the

Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is

inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is

retained.

Table 8-6. Registers 4 And 5 (Polarity Inversion Registers)

Bit

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

Default

Bit

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

Default

The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is

set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this

Table 8-7. Registers 6 And 7 (Configuration Registers)

Bit

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Default

Bit

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

8.3.2.4 Bus Transactions

Data is exchanged between the master and PCA9539 through write and read commands.

8.3.2.4.1 Writes

Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a

logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which

www.ti.com

PCA9539

SCPS130H – AUGUST 2005 – REVISED MARCH 2021

Submit Document Feedback

Product Folder Links: PCA9539

PCA9539DGVR Datasheet(PDF) 21 Page - Texas Instruments

PCA9539DGVR Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL