PCM5101APW datasheet(24/44 Pages) TI2

24 / 44 page

PCM5100A, PCM5101A, PCM5102A

PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1

SLAS859C – MAY 2012 – REVISED MAY 2015

www.ti.com

9.3.5 Reset and System Clock Functions

9.3.5.1 Clocking Overview

The PCM510xA devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio

interface in one form or another.

The data flows at the sample rate (fS). Once the data is brought into the serial audio interface, it gets processed,

interpolated and modulated all the way to 128 × fS before arriving at the current segments for the final digital to

analog conversion.

The serial audio interface typically has 4 connections SCK (system master clock), BCK (bit clock), LRCK (left

right word clock) and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and

create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to

operate with or without an external SCK.

9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)

The PCM510xA requires a system clock to operate the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM510xA system-

clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in

the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384

kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, e.g. 88.2kHZ and

96kHz are detected as "double rate," 32kHz, 44.1kHz and 48kHz will be detected as "single rate".

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the

Negative Charge Pump (NCP) automatically. Table 10 shows examples of system clock frequencies for common

audio sampling rates.

SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in

software mode, available only in the PCM512x, PCM514x, and PCM5242 devices, by configuring various PLL

and clock-divider registers. This programmability allows the device to become a clock master and drive the host

serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz

[LRCK] and 2.8224 MHz [BCK]).

Table 10. System Master Clock Inputs for Audio Related Clocks

System Clock Frequency (fSCK) (MHz)

Sampling

Frequency

64 fS

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

1024 fS

1152 fS

1536 fS

2048 fS

3072 fS

8 kHz

–(1)

1.024(2)

1.536(2)

2.048

3.072

4.096

6.144

8.192

9.216

12.288

16.384

24.576

16 kHz

–(1)

2.048(2)

3.072(2)

4.096

6.144

8.192

12.288

16.384

18.432

24.576

36.864

49.152

32 kHz

–(1)

4.096(2)

6.144(2)

8.192

12.288

16.384

24.576

32.768

36.864

49.152

–(1)

44.1 kHz

–(1)

5.6488(2)

8.4672(2)

11.2896

16.9344

22.5792

33.8688

45.1584

–(1)

48 kHz

–(1)

6.144(2)

9.216(2)

12.288

18.432

24.576

36.864

49.152

–(1)

88.2 kHz

–(1)

11.2896(2)

16.9344

22.5792

33.8688

45.1584

–(1)

96 kHz

–(1)

12.288(2)

18.432

24.576

36.864

49.152

–(1)

176.4 kHz

–(1)

22.579

33.8688

45.1584

–(1)

192 kHz

–(1)

24.576

36.864

49.152

–(1)

384 kHz

24.576

49.152

–(1)

(1)

This system clock rate is not supported for the given sampling frequency.

(2)

This system clock rate is supported by PLL mode.

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