0

10

20

30

40

50

-0.0125

-0.01

-0.0075 -0.005 -0.0025

0

0.0025

Solder Heat Shift Histogram - V

REF (%)

C041

0

10

20

30

40

50

60

-0.0125

-0.01

-0.0075 -0.005 -0.0025

0

0.0025

Solder Heat Shift Histogram - V

BIAS (%)

C040

0

50

100

150

200

250

300

0

50

100

150

200

250

300

350

400

Time (seconds)

C01

12

REF1925, REF1930, REF1933, REF1941

SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017

www.ti.com

Product Folder Links: REF1925 REF1930 REF1933 REF1941

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Copyright © 2014–2017, Texas Instruments Incorporated

8 Parameter Measurement Information

8.1 Solder Heat Shift

The materials used in the manufacture of the REF19xx have differing coefficients of thermal expansion, resulting

in stress on the device die when the device is heated. Mechanical and thermal stress on the device die can

cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is

a common cause of this error.

In order to illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on

each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow

profile. The reflow profile is as shown in Figure 36. The PCB is comprised of FR4 material. The board thickness

is 1.57 mm and the area is 171.54 mm × 165.1 mm.

Figure 36. Reflow Profile

The reference and bias output voltages are measured before and after the reflow process; the typical shift is

displayed in Figure 37 and Figure 38. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are

also possible depending on the size, thickness, and material of the PCB. An important note is that the histograms

display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on

PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the

PCB is exposed to multiple reflows, solder the device in the second pass to minimize device exposure to thermal

stress.

Figure 37. Solder Heat Shift Distribution, VREF (%)

Figure 38. Solder Heat Shift Distribution, VBIAS (%)