RES11A datasheet(40/56 Pages) TI2

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8.2.1.1 Design Requirements

Consider a level-shifting application where a high-side current shunt measurement from an 18V supply rail must

be measured by a 3.3V amplifier and ADC.

PARAMETER

DESIGN GOAL

Input VBUS

18V

ILOAD

300mA (maximum)

RSHUNT

1Ω

ADC full-scale range (target VOUT)

3.3V

Possible VREF voltages

3.3V, 0V

8.2.1.2 Detailed Design Procedure

The design parameters are used with the aforementioned equations to select a nominal target G. When the

possible VREF voltages available in the system are considered, VREF = 0V with G = 9 is found to result in a VMID1

value of 1.8V, well within the input common-mode range of a 3.3V rail-to-rail amplifier such as the OPA392.

When the corresponding RES11A90 is employed, the loss terms ISTATIC1 and ISTATIC2 are nominally 1.80mA

and 1.77mA for ILOAD = 300mA, resulting in an effective floor of 1.77mA for ILOAD. For simplicity, the error

contributions of the INA stage VOS and IB are ignored.

For the INA stage, an integrated TI instrumentation amplifier (IA) can be used. Alternatively, a discrete approach

can be implemented using another RES11A device or devices, and one or more op amps. For this example, an

IA stage is constructed with two channels of a OPA4392 and a second RES11A90 (RIN3, RG3, RIN4, and RG4).

This stage is in turn cascaded with a difference amplifier stage, constructed with the third amplifier channel and

a RES11A00 (RIN5, RG5, RIN6, and RG6). The level-shifting stage gain of 10–1, multiplied by the instrumentation

amplifier stage gain of 10, results in an effective unity-gain transfer function for VSHUNT. Therefore, the differential

output voltage for this stage is approximately 0.3V, with amplifier outputs of 1.936V and 1.634V. After the final

difference amplifier stage gain of G = 10, the common-mode voltage drops out and the maximum value of the

resulting VOUT is nominally 3.0V, compatible with a single-ended 3.3V ADC such as the ADS7046. If desired, the

fourth channel of the OPA4392 can be used to buffer this output signal and serve as a dedicated ADC driver.

SHUNT

BUS

GND

–

EQUIV

IN1

GND

IN2

GND

STATIC1

STATIC2

LOAD

LOAD + ISTATIC2

LOAD + ISTATIC1 + ISTATIC2

MID1

MID2

LOAD

SHUNT

–

OPA392

–

IN4

IN3

OPA392

IN6

GND

IN5

–

OPA392

–

OPA392

OUT

Figure 8-17. High-Side Current Shunt Common-Mode Shifting Circuit

RES11A

SLPS785A – DECEMBER 2023 – REVISED OCTOBER 2025

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