INDP3P

18

INDP3N

19

TEST2/SDA

22

DPEN/HPDIN

23

RSVD4

7

VCC

6

RSVD1

3

DPEQ1

2

INDP0N

10

OUTDP3N

31

AUXN

25

INDP2N

16

INDP2P

15

INDP1P

12

SNOOPENZ/RSVD8

29

VCC

28

INDP0P

9

HPDIN/RSVD9

32

RSVD6

26

INDP1N

13

OUTDP2N

34

RSVD10

35

OUTDP1N

36

OUTDP1P

37

RSVD11

38

OUTDP0N

39

OUTDP0P

40

TPAD

41

RSVD7

27

OUTDP3P

30

DPEQ0/A1

14

A0

11

VCC

20

TEST1/SCL

21

AUXP

24

I2C_EN

17

VCC

1

OUTDP2P

33

RSVD5

8

RSVD2

4

RSVD3

5

U1

TDP142RNQ

0.1uF

C6

0.1uF

C7

0.1uF

C8

0.1uF

C9

0.1uF

C10

0.1uF

C11

0.1uF

C12

0.1uF

C13

10k

R3

10k

R4

GND

OUTDP0P

OUTDP0N

OUTDP1P

OUTDP1N

OUTDP2P

OUTDP2N

OUTDP3P

OUTDP3N

GND

CAD

HPDIN

DPEQ1

DPEQ2

A0

AUX_P

AUX_N

I2C_EN

1k

R8

1k

R9

1k

R10

1k

R12

1k

R13

GND

GND

GND

3P3V

3P3V

I2C_EN

DPEQ0

DPEQ1

20k

R11

20k

R14

10uF

C1

0.1uF

C2

0.1uF

C3

0.1uF

C4

0.1uF

C5

3P3V

3V3P

Board_3P3V

220 ohm

FB

HPDIN

AUX_P

AUX_N

CAD

1M

R1

GND

5M

R2

ML2_N

ML2_P

ML3_N

ML3_P

ML0_N

ML0_P

ML1_N

ML1_P

ML0_P

ML0_N

ML1_P

ML1_N

ML2_P

ML2_N

ML3_P

ML3_N

ML0_P

ML0_N

ML1_P

ML1_N

ML2_P

ML2_N

ML3_P

ML3_N

AUX_P

AUX_N

HPD

DisplayPort Sink

0.1uF

C14

0.1uF

C15

1M

R6

1M

R7

3P3V

GND

HPDIN

ML1_P

9

ML1_N

7

ML0_P

12

ML0_N

10

ML3_P

3

ML3_N

1

ML2_P

6

ML2_N

4

DP_PWR

20

AUX_P

15

AUX_N

17

HPD

18

CONFIG1

13

GND

2

GND

5

GND

8

GND

11

CONFIG2

14

GND

16

GND

21

GND

22

GND

23

GND

24

RTN

19

DisplayPort Recepticle Sink

GND

AUX_P

AUX_N

1k

R5

10k

R15

3V3P

Note:

AC-coupled is needed if there is no

ac-coupled on the other end of source side.

Copyright © 2017, Texas Instruments Incorporated

24

TDP142

SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

www.ti.com

Product Folder Links: TDP142

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Copyright © 2017–2019, Texas Instruments Incorporated

9.2.2 Sink Application Implementation

Figure 19 is the schematic for the Sink application, and the left side of TDP142 is connected to DisplayPort

receptacle and the right side of TDP142 is connected to Scaler or DisplayPort sink.

Figure 19. The Block diagram of DisplayPort Sink Application

9.2.2.1 Design Requirements

For this design example, the parameters listed in Table 13 are used.

Table 13. Design Parameters

PARAMETER

VALUE

Maximum Operating data rate

(RBR, HBR, HBR2, or HBR3)

HBR3 (8.1Gbps)

Supply voltage

3.3V

Trace length/width of C

12 inch/ 6 mil

Trace length/width of D

2 inch/ 6 mil

Main link AC decoupling capacitor

(75 nF to 265 nF)

Recommend 100 nF

Control mode (I2C or GPIO)

GPIO (I2C_EN = 0)