¼

16-BitShiftRegister(1Bit

16Channels)

´

OutputOn/OffDataLatch(1Bit

16Channels)

´

16Bits

ToConstant-CurrentDriverControlBlock

¼

SOUT

13

12

3

2

LSB

On/OffData

for

OUT3

On/OffData

for

OUT2

On/OffData

for

OUT13

On/OffData

for

OUT12

SIN

SCLK

¼

13

12

3

2

LSB

LAT

15

14

On/OffData

for

OUT15

On/OffData

for

OUT14

15

14

1

0

On/OffData

for

OUT1

On/OffData

for

OUT0

1

0

MSB

MSB

On/OffData

for

OUT13

On/OffData

for

OUT12

On/OffData

for

OUT15

On/OffData

for

OUT14

11

11

4

4

On/OffData

for

OUT3

On/OffData

for

OUT2

On/OffData

for

OUT1

On/OffData

for

OUT0

TLC59282

www.ti.com

SBVS152C

– DECEMBER 2010 – REVISED OCTOBER 2011

REGISTER CONFIGURATION

The TLC59282 has a 16-bit shift register and an output on/off data latch. Both the shift register and data latch

are 16 bits long and are used to turn the constant-current outputs on and off. Figure 16 shows the shift register

and data latch configuration. The data at the SIN pin are shifted in to the LSB of the 16-bit shift register at the

rising edge of the SCLK pin; SOUT data change at the rising edge of SCLK.

The output on/off data in the 16-bit shift register continue to transfer to the output on/off data latch while LAT is

high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data latch

are also changed. The data in the data latch are held when LAT is low. When the IC initially powers on, the data

in the output on/off shift register and latch are not set to the default values; on/off control data must be written to

the on/off control data latch before turning the constant-current output on. BLANK should be high when the IC is

powered on because the constant-current may be turned on at that time as a result of random values in the

on/off data latch. All constant-current outputs are forced off when BLANK is high. The OUTn on/off are controlled

by the data in the output on/off data latch. The timing diagram and truth table for writing data are shown in

Figure 17 and Table 3.

Figure 16. 16-Bit Shift Register and Output On/Off Data Latch Configuration

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© 2010–2011, Texas Instruments Incorporated

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