8

TLV313, TLV2313, TLV4313

SBOS753B – JUNE 2016 – REVISED FEBRUARY 2017

www.ti.com

Product Folder Links: TLV313 TLV2313 TLV4313

Submit Documentation Feedback

Copyright © 2016–2017, Texas Instruments Incorporated

(1)

Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over-

temperature limits are based on characterization and statistical analysis.

7.7 Electrical Characteristics: 5.5 V

At TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

0.75

3

mV

dVOS/dT

Input offset voltage vs

temperature

TA = –40°C to 125°C

2

μV/°C

PSRR

Power-supply rejection ratio

74

90

dB

INPUT VOLTAGE RANGE

VCM

Common-mode voltage range

No phase reversal, rail-to-rail input

(V–) – 0.2

(V+) + 0.2

V

CMRR

Common-mode rejection ratio

(VS–) – 0.2 V < VCM < (VS+) – 1.3 V

85

dB

VCM = –0.2 V to 5.7 V

64

80

dB

INPUT BIAS CURRENT

IB

Input bias current

±1

pA

IOS

Input offset current

±1

pA

NOISE

Input voltage noise (peak-to-

peak)

f = 0.1 Hz to 10 Hz

6

μVPP

en

Input voltage noise density

f = 10 kHz

22

nV/

√Hz

f = 1 kHz

26

nV/

√Hz

in

Input current noise density

f = 1 kHz

5

fA/

√Hz

INPUT CAPACITANCE

CIN

Differential

1

pF

Common-mode

5

pF

OPEN-LOOP GAIN

AOL

Open-loop voltage gain

0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ

104

dB

0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ

100

110

dB

Phase margin

VS = 5.0 V, G = +1

65

°