ADG714/ADG715

–12–

REV. B

FREQUENCY – Hz

30k

–90

–80

–60

–40

100k

1M

10M

100M

–100

–70

–50

TPC 13. Crosstalk vs. Frequency

VOLTAGE – V

–3

10

0

–20

–15

–10

–5

5

–2

–1

0

1

2

3

4

5

TPC 14. Charge Injection vs. Source/Drain Voltage

TEMPERATURE – C

10

20

30

70

40

45

40

60

50

80

35

30

25

20

15

10

5

0

GENERAL DESCRIPTION

The ADG714 and ADG715 are serially controlled, octal SPST

switches, controlled by either a 2- or 3-wire interface. Each bit

of the 8-bit serial word corresponds to one switch of the part. A

Logic 1 in the particular bit position turns on the switch, while a

Logic 0 turns the switch off. Because each switch is independently

controlled by an individual bit, this provides the option of having

any, all, or none of the switches ON.

When changing the switch conditions, a new 8-bit word is writ-

ten to the input shift register. Some of the bits may be the same

as the previous write cycle, as the user may not wish to change

the state of some switches. To minimize glitches on the output

of these switches, the part cleverly compares the state of switches

from the previous write cycle. If the switch is already in the

ON condition, and is required to stay ON, there will be minimal

glitches on the output of the switch.

POWER-ON RESET

On power-up of the device, all switches will be in the OFF con-

dition and the internal shift register is filled with zeros and will

remain so until a valid write takes place.

SERIAL INTERFACE

3-Wire Serial Interface

The ADG714 has a 3-wire serial interface (

SYNC, SCLK, and

DIN), that is compatible with SPI, QSPI, MICROWIRE

interface standards and most DSPs. Figure 1 shows the tim-

ing diagram of a typical write sequence.

Data is written to the 8-bit shift register via DIN under the con-

trol of the

SYNC and SCLK signals. Data may be written to

the shift register in more or less than eight bits. In each case

the shift register retains the last eight bits that were written.

When

SYNC goes low, the input shift register is enabled. Data

from DIN is clocked into the shift register on the falling edge of

SCLK. Each bit of the 8-bit word corresponds to one of the eight

switches. Figure 3 shows the contents of the input shift register.

Data appears on the DOUT pin on the rising edge of SCLK

suitable for daisy chaining, delayed of course by eight bits. When

all eight bits have been written into the shift register, the

SYNC

line is brought high again. The switches are updated with the

new configuration and the input shift register is disabled. With

SYNC held high, the input shift register is disabled, so further data

or noise on the DIN line will have no effect on the shift register.

S8

S7

S6

S5

S4

S3

S2

S1

DB7 (MSB)

DB0 (LSB)

DATA BITS

Figure 3. Input Shift Register Contents

SERIAL INTERFACE

2-Wire Serial Interface

The ADG715 is controlled via an I

This device is connected to the bus as a slave device (no clock is

generated by the switch).

The ADG715 has a 7-bit slave address. The five MSBs are 10010

and the two LSBs are determined by the state of the A0 and

A1 pins.