TMS320F28027 datasheet(22/147 Pages) TI2

22 / 147 page

over recommended operating conditions (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

IIH

Input current

(high level)

Pin with pullup

enabled

VDDIO = 3.3 V, VIN = VDDIO

±2

μA

Pin with pulldown

enabled

VDDIO = 3.3 V, VIN = VDDIO

IOZ

Output current, pullup or pulldown

disabled

VO = VDDIO or 0 V

±2

μA

Input capacitance

VDDIO BOR trip point

Falling VDDIO

2.42

2.65

3.135

VDDIO BOR hysteresis

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

400

800

μs

VREG VDD output

Internal VREG on

1.9

(1)

When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(VDD) go out of range.

TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026

TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023

TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200

SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021

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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1

TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-

Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200

TMS320F28027 Datasheet(PDF) 22 Page - Texas Instruments

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