ADF5611BCCZ datasheet(21/48 Pages) AD

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Data Sheet

ADF5611

THEORY OF OPERATION

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Charge Pump

The charge pump, controlled by the PFD, forces sink (down) or

source (up) current pulses onto the CP pin, which must be connect-

ed to an appropriate loop filter. See Figure 51 for a simplified

schematic of the charge pump.

Figure 51. Simplified Charge Pump Schematic

The output current magnitude, ICP, can be set from 0.2mA to 3.2mA

using the CP_I bits (Register 0x021, Bits[3:0]). A larger ICP can

result in lower in-band noise due to the lower impedance of the

loop filter components, while a smaller ICP can result in better spuri-

ous performance. See Table 7 for the charge pump programming

values.

Table 7. CP Programming

CP_I, Bits[3:0]

ICP (mA)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

3.2

Charge Pump Test Mode

When the charge pump test mode EN_CPTEST bit (Register

0x02B, Bit 2) is set to 1, it allows the CP_UP and CP_DOWN

bits (Register 0x02B, Bit 0 and Bit 1, respectively) to enforce a

constant ICP source or sink current, respectively, on the CP pin.

These bits can be used as an aid to debug issues related to PLL

during the hardware and software development phase of a project.

For normal operation, set EN_CPTEST, CP_UP, and CP_DOWN to

0. See Table 8 for applicable charge pump test mode.

Table 8. Charge Pump Test Mode

EN_CPTEST

CP_UP

CP_DOWN

CP Pin State Debug Test

High-Z

VCO open loop

~V3.3V_CP

Charge pump

output voltage

verification

~GND

Charge pump

output voltage

verification

Normal

operation

Not applicable

Charge Pump Bleed Current Optimization

A small programmable constant charge pump current, known as

bleed current, can be used to optimize the phase noise and

fractional spurious signals in fractional mode, which also changes

the propagation delay from the XREFP input pin to the RFOUT,

PDIV_OUT, and NDIV_OUT output pins.

Configure the EN_BLEED bit (Register 0x01E, Bit 6) to 1 to enable

the bleed current. If the BLEED_POL bit (Register 0x01E, Bit 0)

is set to 1, a constant source current is applied to the CP pin.

Conversely, if the BLEED_POL bit is adjusted to 0, a constant sink

current is applied to the CP pin.

The 8-bit BLEED_I bits (Register 0x01D, Bits[7:0]) are used to opti-

mize the spurious performance of the ADF5611. The bleed current,

BLEED_I, is calculated and configured based on the required bleed

time (tBLEED) at a given VCO frequency, ICP, and fPFD as shown in

the following equations:

tBLEED= 42×VCO

IBLEED=tBLEED×fPFD×ICP

BLEED_I= IBLEED3.125μA

Lock Detector

The lock detector uses internal signals from the PFD to measure

the phase difference between the output signal of the reference di-

vider (RCLK) and the output signal of the feedback divider (NCLK)

in Figure 50. This detector is enabled by configuring the PD_LD bit

(Register 0x027, Bit 3) to 0, and both the EN_LOL and EN_LDWIN

bits (Register 0x02A, Bit 5 and Bit 4, respectively) to 1. The output

of the lock detector can be accessed either through the LOCKED

bit (Register 0x048, Bit 0), or via the SDO pin (Pin 19) by setting the

EN_MUXOUT bit (Register 0x02B, Bit 3) to 1 and programming the

MUXOUT bits (Register 0x02B, Bits[7:4]) to 1 (LKDET).

The PFD RCLK and NCLK phase difference must be less than the

phase difference lock window time, tLDWIN, for a set number of PFD

cycles before the lock detector output indicates the PLL has locked.

The desired number of PFD cycles varies depending on whether

the lock detect accuracy or speed is prioritized. See Table 9 to set

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