LOGIC DIAGRAM

TRUTH TABLE

RESET

CLOCK

DATA INPUT DISABLE

DATA

D

NEXT STATE

OUTPUT G

G1

G2

1X

X

X

X

0

0

0

X

XXQ

NC

0

1

XXQ

NC

0X

1

X

Q

NC

00

0

1

1

00

0

0

0

0

1

X

XXQ

NC

0

X

XXQ

NC

When either Output DisableM or N is high, theoutputs aredisablesd (high impedance state): however sequential operation of the flip-flopis not affected.

1 = High Level, 0 = Low Level, X = Don’t Care, NC = No Change

HCC/HCF4076B

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