EN = 10 V / div

SS = 5 V / div

V = 500 mV / div

O

Time = 2 msec / div

V = 50 mV / div (-950 mV dc offset)

O

I = 1 A / div (0.75 to 2.25 A load step,

slew rate = 1 A / µsec)

O

Time = 50 µsec / div

IN

OUT

OUT

=

Co(RMS)

IN

O

SW

V

x (V

- V

)

12 x V

x L

x

I

f

13

TPS54328

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SLVSAN2D – NOVEMBER 2010 – REVISED AUGUST 2016

Product Folder Links: TPS54328

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Copyright © 2010–2016, Texas Instruments Incorporated

For this design example, the calculated peak current is 3.49 A and the calculated RMS current is 3.01 A. The

inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of

11 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS54328 is intended for use

with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 8 to

determine the required RMS current rating for the output capacitor.

(8)

For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.

The calculated RMS current is 0.271 A and each output capacitor is rated for 4 A.

8.2.2.3 Input Capacitor Selection

The TPS54328 requires an input decoupling capacitor and a bulk capacitor is required depending on the

application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. TI recommends an

additional 0.1-µF capacitor from VIN to ground to improve the stability of the over-current limit function. The

capacitor voltage rating requires to be greater than the maximum input voltage.

8.2.2.4 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST and SW pin for proper operation. TI

recommends using a ceramic capacitor.

8.2.2.5 VREG5 Capacitor Selection

A 1-µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. TI

recommends using a ceramic capacitor.

8.2.3 Application Curves

Figure 7. 1.05 V, Load Transient Response

Figure 8. Start-up Waveform