CL

(see Note A)

TEST CIRCUIT

S1

2 × VDD

Open

GND

RL

RL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low

, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

50 Ω

VG1

VDD

DUT

50 Ω

VIN

50 Ω

VG2

50 Ω

VI

TEST

RL

S1

V∆

CL

VDD

Vin

tPLZ/tPZL

3.3 V

2 × VDD

200 Ω

GND

10 pF

0.3 V

Input Generator

Input Generator

VO

tPHZ/tPZH

3.3 V

GND

200 Ω

VDD

10 pF

0.3 V

tPZL

VOH − 0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VDD/2

VDD/2

Output Control

(VIN)

1.25 V

2.5 V

VOH

VOL + 0.3 V

VOH

VOL

0 V

1.25 V

tPZH

tPLZ

tPHZ

Output

Waveform 2

S1 at GND

(see Note B)

Output

Waveform 1

S1 at 2 x VDD

(see Note B)

VOL

VO

VI

VO

TS3V712E

www.ti.com

SCDS292A – JANUARY 2010 – REVISED JULY 2010

PARAMETER MEASUREMENT INFORMATION

Figure 5. Test Circuit and Voltage Waveforms

Copyright © 2010, Texas Instruments Incorporated

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