| Electronic Components Datasheet Search |
|
MLX90333 Datasheet(PDF) 13 Page - Melexis Microelectronic Systems |
|
|
|||||||||||||||||||||||||||||
MLX90333 Datasheet(HTML) 13 Page - Melexis Microelectronic Systems |
|
13 / 38 page ![]() MLX90333 Triaxis 3D-Joystick Position Sensor 3901090333 Page 13 of 38 Data Sheet Rev. Preliminary May 07 7. MLX90333 Electrical Specification DC Operating Parameters at VDD = 5V (unless otherwise specified) and for TA as specified by the Temperature suffix (K). Parameter Symbol Test Conditions Min Typ Max Units Nominal Supply Voltage VDD 4.5 5 5.5 V Supply Current(3) Idd Slow mode(4) Fast mode(4) 8.5 13.5 11 16 mA mA POR Level VDD POR Supply Under Voltage 2 2.7 3 V Output Current Both outputs OUT 1 & OUT 2 Iout Analog Output mode PWM Output mode -8 -20 8 20 mA mA Output Short Circuit Current Both outputs OUT 1 & OUT 2 Ishort Vout = 0 V Vout = 5 V Vout = 14 V (TA = 25°C) 12 12 24 15 15 45 mA mA mA Output Load Both outputs OUT 1 & OUT 2 RL Pull-down to Ground Pull-up to 5V(5) 1 1 10 10 ∞(6) ∞(6) k Ω k Ω Vsat_lo Pull-up load RL ≥ 10 kΩ 3 %VDD Analog Saturation Output Level Both outputs OUT 1 & OUT 2 Vsat_hi Pull-down load RL ≥ 10 kΩ 96 %VDD VsatD_lo Pull-up Low Side RL ≥ 10 kΩ Push-Pull (IOUT = -20mV) 1.5 %VDD Digital Saturation Output Level Both outputs OUT 1 & OUT 2 VsatD_hi Push-Pull (IOUT = 20mV) 97 %VDD Diag_lo Pull-down load RL ≥ 10 kΩ Pull-up load RL ≥ 10 kΩ 1 1.5 %VDD Active Diagnostic Output Level Both outputs OUT 1 & OUT 2 Diag_hi Pull-down load RL ≥ 10 kΩ Pull-up load RL ≥ 10 kΩ 97 98 %VDD BVSSPD Broken VSS& Pull-down load RL ≤ 10 kΩ 4(7) %VDD BVSSPU Broken VSS(8) & Pull-up load RL ≥ 1kΩ 99 100 %VDD BVDDPD Broken VDD(8) & Pull-down load RL ≥ 1kΩ 0 1 %VDD Passive Diagnostic Output Level Both outputs OUT 1 & OUT 2 (Broken Track Diagnostic) (7) BVDDPU Broken VDD & Pull-up load to 5V No Broken Track diagnostic %VDD Clamp_lo Programmable 0 100 %VDD(9) Clamped Output Level Both outputs OUT 1 & OUT 2 Clamp_hi Programmable 0 100 %VDD(9) 3 For the dual version, the supply current is multiplied by 2 4 See section 14.5.1 for details concerning Slow and Fast mode 5 Applicable for output in Analog and PWM (Open-Drain) modes 6 RL < ∞ for output in PWM mode 7 For detailed information, see also section 15 9 Clamping levels need to be considered vs the saturation of the output stage (see Vsat_lo and Vsat_hi) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |