MLX71122 datasheet(21/44 Pages) MELEXIS

21 / 44 page

INA

MLX71122

300 to 930MHz

FSK/FM/ASK Receiver

39010 71122

Page 21 of 44

Data Sheet

Rev. 007

Oct/07

3.4.4

IF Amplifier (IFA)

After passing the IF filter the receiving signal is amplitude limited by means of a high gain limiting amplifier.

Its small signal gain is about 68dB. A received signal strength indicator (RSSI) voltage is generated in the IF

amplifier. It is available at pin RSSI. The voltage at this pin is proportional to the input level of the receiver (in

dB scales). By using this RSSI output signal the incoming signal strength of different transmitters can be

determined. The same RSSI signal is used for receiving ASK modulated signals if MODSEL (see 4.1.6) is

HIGH.

The IFA generates two digital signals RSSIL and RSSIH that indicate the level range of the RSSI voltage. If

the level is in the lower quarter of the RSSI voltage range then both signals are LOW. If it is in the upper

quarter of the RSSI range then both signals are HIGH. In between, the RSSIL signal is HIGH and RSSIH is

LOW. Both values can be read out from register R7 of the IC (see 4.1.8). These two signals are also used

for the AGC feature.

3.4.5

Automatic Gain Control (AGC)

The Automatic Gain Control (AGC) can be activated in SPI mode with AGCEN (see 4.1.4). By default, it is

turned off. It uses the RSSIH and RSSIL signals of the IF amplifier to determine whether the gain has to be

increased or decreased. The gain will be decreased beginning with the gain of the last stage. The gain

increase works vice versa. The AGC circuit controls the gain of the LNA, and of mixer 1 and mixer 2. To

avoid rapid gain switching, caused by short signal strength fluctuations or during ASK reception, the gain

control operates with a time delay that can be programmed via AGCDEL (see 4.1.4). The time delay also

depends on the PFD frequency of the IF filter auto-tuning circuit. There is no delay by default. AGCMODE

(see 4.1.5), a second setting, determines whether the delay is applied for gain increase and decrease or only

for gain increase. By default, a delay for increase and decrease is used.

3.4.6

FSK Demodulator

FSK reception is turned on if bit MODSEL in register R5 is set to LOW (default). The demodulator is

completely internally implemented, so no external, expensive discriminator device is needed. The used FSK

demodulator is based on time delay elements and a mixer. The delay path provides a phase shift of 90

degrees to the original IF signal. The average of the phase shift is controlled, so that the input frequency

acceptance range is wider than the IF filter bandwidth of 230kHz. The gain of the demodulator can be

changed with bit DEMGAIN (see 4.1.1). It can be at low gain with about 4mV/kHz (default) or at high gain

with about 15mV/kHz. High gain should only be used for small FSK/FM deviations of up to ±15kHz, because

the demodulator gets nonlinear at larger FM/FSK deviations.

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