Figure 4 below describes the basic relationship between

settling time (T

tance, C

Figure 5 shows the resulting changes in bandwidth and slew

rate for increasing values of C

CLC532 output can be approximated as:

where.... n

BW

Power Supplies and Grounding

Proper power supply bypassing and grounding is essential

to the CLC532’s operation. 0.1µF to .1µF ceramic chip ca-

pacitor should be located very close to the individual power

supply pins. Larger +6.8µF tantalum capacitors should be

used within a few inches of the CLC532. The ground con-

nections for these larger by-pass capacitors should be sym-

metrically located relative the CLC532 output load ground

connection. Harmonic distortion can be heavily influenced by

non-symmetric decoupling capacitor grounding. The smaller

chip capacitors located directly at the power supply pins are

not particularly susceptible to this effect.

Separation of analog and digital ground planes is not recom-

mended. In most cases, a single low impedance ground

plane will provide the best performance. In those special

cases requiring separate ground planes, the following table

indicates the signal and supply ground connections.

Pin

Functions

Ground Return

1,3

Shield/Supply Returns

Supplies and

Inputs

5D

D

only

Input Shielding

The CLC532 has been designated for use in high speed

wide dynamic range systems. Guarding traces and the use

of the ground pins separating the analog inputs are recom-

mended to maintain high isolation (

Figure 6). Likely sources

of noise and interference that may couple onto the inputs,

are the logic signals and power supplies to the CLC532.

Other types if clock and signal traces should not be over-

looked, however.

The general rule in maintaining isolation has two facets,

minimize the primary return ground current path impedances

back to the respective signal sources, while maximizing the

impedance associated with common or secondary ground

current return paths. Success or failure to optimize input

signal isolation can be measured directly as the isolation

between the input channels with the CLC532 removed from

circuit. The channel-to -channel isolation of the CLC532 can

never be better than the isolation level present at its inputs.

Special attention must be paid to input termination resistors.

Minimizing the return current path that is common to both of

the input termination resistors is essential. In the event that a

ground return current from one input termination resistor is

able to find a secondary path back to its signal source (which

also happens to be common with either the primary or sec-

ondary return path for the second input termination resistor),

a small voltage can appear across the second input termi-

nation resistor. The small voltage seen across the second

input termination resistor will be highly correlated with the

signal generating the initial return currents. This situation will

severely degrade channel-to-channel isolation at the input of

the CLC532, even if the CLC532 were removed from circuit.

Poor isolation at the input will be transmitted directly to the

output.

Use of “small” value input termination resistors will also

improve channel-to-channel isolation. However, extremely

Ω) tend to stress the driving source’s ability

to provide a high-quality input signal to the CLC532. Higher

values tend to aggravate any layout dependent crosstalk.

75

Ω to 50Ω is a reasonable target, but the lower the better.

DS012716-39

FIGURE 4. Settling Time and R

DS012716-41

FIGURE 5. C

Response

Channel A

Connector

Channel B

Connector

Chip Resistors

Pin 1

DS012716-42

FIGURE 6. Alternate Layout Using Guard Ring

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