AD8197B

Rev. 0 | Page 21 of 28

PARALLEL INTERFACE CONFIGURATION REGISTERS

The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and

PP_OCL pins. This interface is accessible only after the part is reset and before any registers are accessed using the serial control interface.

Because most systems use serial control for the input termination resistors, the parallel control interface is limited to controlling the

AD8197B status after reset and before serial logic control. The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).

Table 18. Parallel Interface Register Map

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

High speed

switch enable

High speed source select

High Speed Device

Modes

PP_EN

0

0

0

0

PP_CH[1]

PP_CH[0]

Auxiliary switch

enable

Auxiliary switch source select

Auxiliary Device

Modes

1

0

0

0

0

PP_CH[1]

PP_CH[0]

Input term.

select

(terminations

always open in

parallel control

mode)

Receiver Settings

1

Source A and Source B input termination select (No parallel control termination, always open)

Input Termination

Resistor Control.1

0

0

0

0

0

0

0

0

Source C and Source D input termination select (No parallel control termination, always open)

Input Termination

Resistor Control 2

0

0

0

0

0

0

0

0

Source A and Source B input equalization level select

Receive Equalizer 1

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

Source C and Source D input equalization level select

Receive Equalizer 2

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

PP_EQ

Output pre-emphasis

level select

Output termination

on/off select

Output current

level select

Transmitter Settings

PP_PE[1]

PP_PE[0]

PP_OTO

PP_OCL