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RF3166
Rev A3 DS061031
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT.
By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the
PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power
from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing
switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accor-
dance with VRAMP.
The switching transients due to low battery conditions are regulated by the VBATT tracking circuit. The VBATT tracking circuit con-
sists of a feedback loop that detects FET saturation. As the FET approaches saturation, the limiter adjusts the VRAMP voltage in
order to ensure minimum switching transients. The VBATT tracking circuit is integrated into the CMOS controller and requires no
additional input from the user.
Due to reactive output matches, there are output power variations across frequency. There are a number of components that
can make the effects greater or less. Power variation straight out of the RF3166 is shown in the tables below.
The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is
some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers
due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3166 does
not use a directional coupler with a diode detector, these variations do not occur.
Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS
and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers.
The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc
voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthe-
sizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations pre-
sented to the VCO.
The RF3166 presents a very constant load to the VCO. This is because all stages of the RF3166 are run at constant bias. As a
result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier.
Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of out-
put power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 2),
(Eq. 2)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3166 is kept constant the gain
in the first stage is always high and the overall noise power is not increased when decreasing output power.
Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop
involves trade-offs affecting stability, transient spectrum and burst timing.
In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth also
varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as
1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope
regions which often causes instability at high slope regions.
The RF3166 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to
power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector volt-
age do not vary.
F
TOT
F1
F21
–
G1
----------------
F31
–
G1 G2
⋅
-------------------
++
=
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