CY28159

Clock Generator for Serverworks Grand Champion Chipset

Applications

Rev 1.0, November 24, 2006

Page 1 of 12

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

1CY28159

Features

• Eight differential CPU clock outputs

• One PCI output

• One 14.31818 MHz reference clock

• Two 48 MHz clocks

• External resistor for current reference

• Selection logic for differential swing control, test mode,

Hi-Z, power-down and spread spectrum

• 48-pin SSOP and TSSOP packages

Table 1. Frequency Selection

SEL 100/133

S0

S1

CPU(0:7), CPU#(0:7)

3V33

48M(0,1)

Notes

0

0

0

100 MHz

33.3MHz

48 MHz

Normal Operation

0

0

1

100 MHz

33.3MHz

Disable

Test Mode(recommended)

0

1

0

100 MHz

Disable

Disable

Test Mode (optional)

0

1

1

Hi-Z

Hi-Z

Hi-Z

Hi-Z all outputs

1

0

0

133.3MHz

33.3MHz

48 MHz

Optional

1

0

1

133.3MHz

33.3MHz

Disable

Optional

1

1

0

200MHz

33.3MHz

48 MHz

o7ptional

1

1

1

N/A

N/A

N/A

Reserved

Table 2.

BlockDiagram

Pin Configuration

OSC

VCO

I

Control

VDDI

I_Ref

VSSI

REF

CPU (0:7)

CPU (0:7)#

48M(0,1)/S(0,1)

VDDL

3V33

VSSL

SSCG#

SEL100/133

XOUT

XIN

MultSel(0:1)

PD#

S(0,1)

3V33

VDD

48M0/S0

48M1/S1

VSS

VDD

CPU0

CPU0#

VSS

CPU1

CPU1#

VDD

CPU2

CPU2#

VSS

CPU3

CPU3#

VDD

REF

SSCG#

VSS

XIN

XOUT

VDD

SEL100/133

VSS

VDDA

VSSA

PD#

VDD

CPU4

CPU4#

VSS

CPU5

CPU5#

VDD

CPU6

CPU6#

VSS

CPU7

CPU7#

VDD

MULT0

MULT1

VSS

VSSA

IREF

VDDA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25