LM4871 datasheet(11/16 Pages) NSC

11 / 16 page

Application Information (Continued)

lows the LM4871 to reproduce peaks in excess of 1W with-

out producing audible distortion. At this time, the designer

must make sure that the power supply choice along with the

output impedance does not violate the conditions explained

in the Power Dissipation section.

Once the power dissipation equations have been addressed,

the required differential gain can be determined from Equa-

tion 4.

(4)

f/Ri =AVD/2

(5)

From Equation 4, the minimum A

VD is 2.83; use AVD =3.

Since the desired input impedance was 20k

Ω, and with a

VD impedance of 2, a ratio of 1.5:1 of Rf to Ri results in an

allocation of R

i = 20k

Ω and R

f = 30k

Ω. The final design step

is to address the bandwidth requirements which must be

stated as a pair of −3dB frequency points. Five times away

from a −3dB point is 0.17dB down from passband response

which is better than the required ±0.25dB specified.

L = 100Hz/5 = 20Hz

H = 20kHz*5= 100kHz

As stated in the External Components section, R

i in con-

junction with C

i create a highpass filter.

≥ 1/(2π*20kΩ*20Hz) = 0.397µF; use 0.39µF

The high frequency pole is determined by the product of the

desired frequency pole, f

H, and the differential gain, AVD.

With a A

VD = 3 and fH = 100kHz, the resulting GBWP =

150kHz which is much smaller than the LM4871 GBWP of

4MHz. This figure displays that if a designer has a need to

design an amplifier with a higher differential gain, the

LM4871 can still be used without running into bandwidth

limitations.

Demonstration Board Layout

10000829

FIGURE 2. Recommended LD PC Board Layout:

Component-Side Silkscreen

10000830

FIGURE 3. Recommended LD PC Board Layout:

Component-Side Layout

10000831

FIGURE 4. Recommended LD PC Board Layout:

Bottom-Side Layout

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