ADC12040 datasheet(13/19 Pages) NSC

13 / 19 page

Functional Description

Operating on a single +5V supply, the ADC12040 uses a

pipeline architecture and has error correction circuitry to help

ensure maximum performance. The differential analog input

signal is digitized to 12 bits.

The reference input is buffered to ease the task of driving

that pin and the output word rate is the same as the clock

frequency. The analog input voltage is acquired at the rising

edge of the clock and the digital data for a given sample is

delayed by the pipeline for 6 clock cycles. A logic high on the

power down (PD) pin reduces the converter power con-

sumption to 40 mW.

Applications Information

1.0 OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC12040:

4.75V

≤ V

≤ 5.25V

D =VA

2.35V

≤ V

100 kHz

≤ f

CLK

≤ 50 MHz

1.0V

≤ V

REF

≤ 2.2V

0.5V

≤ V

≤ 3.0V

≤ V

≤ (V

A − 1.0V)

REF and VCM must be such that the signal swing remains

within the limits of 0V to V

1.1 Analog Inputs

The ADC12040 has two signal input pins, V

IN+ and VIN−,

forming a differential input pair, and one reference input pin,

REF.

1.2 Reference Pins

The ADC12040 is designed to operate with a 2.0V reference,

but performs well with reference voltages in the range of

1.0V to 2.2V. Lower reference voltages will decrease the

signal-to-noise ratio (SNR). Increasing the reference voltage

(and the input signal swing) beyond 2.2V will degrade THD

for a full-scale input. It is important that all grounds associ-

ated with the reference voltage and the input signal make

connection to the ground plane at a single point to minimize

the effects of noise currents in the ground path.

The three Reference Bypass Pins (V

RP,VRM and VRN) are

made available for bypass purposes only. These pins should

each be bypassed to ground with a 0.1 µF capacitor. DO

NOT LOAD these pins.

1.3 Signal Inputs

The signal inputs are V

IN+ and VIN−. The input signal, VIN,is

defined as

IN =(VIN+) – (VIN−)

Figure 2 shows the expected input signal range.

Note that the common mode input voltage range is 1V to 3V

with a nominal value of V

A/2. The input signals should re-

main between ground and 4V.

The Peaks of the individual input signals (V

IN+ and VIN−)

should each never exceed the voltage described as

IN+, VIN−=VREF/2+VCM

≤ 4V

to maintain THD and SINAD performance.

The ADC12040 performs best with a differential input with

each input centered around a V

CM. The peak-to-peak volt-

age swing at V

IN+ and VIN− should EACH not exceed the

value of the reference voltage or the output data will be

clipped. The two input signals should be exactly 180˚ out of

phase from each other and of the same amplitude. For single

frequency inputs, angular errors result in a reduction of the

effective full scale input. For a complex waveform, however,

angular errors will result in distortion.

For angular deviations of up to 10 degrees from these two

signals being 180 out of phase, the full scale error in LSB

can be described as approximately

FS =4096(1-sin (90˚ + dev))

Where dev is the angular difference between the two signals

having a 180˚ relative phase relationship to each other (see

Figure 3). Drive the analog inputs with a source impedance

less than 100

Ω.

For differential operation, each analog input signal should

have a peak-to-peak voltage equal to the input reference

voltage, V

REF, and be centered around a VCM.

TABLE 1. Input to Output Relationship – Differential

Input

IN+

IN−

Output

CM −VREF/2

CM +VREF/2

0000 0000 0000

CM −VREF/4

CM +VREF/4

0100 0000 0000

1000 0000 0000

CM +VREF/2

CM −VREF/4

1100 0000 0000

CM +VREF/2

CM −VRE/2F

1111 1111 1111

20014811

FIGURE 2. Expected Input Signal Range

20014812

FIGURE 3. Angular Errors Between the Two Input

Signals Will Reduce the Output Level

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