DS90C387 Pin Descriptions — FPD Link Transmitter

Pin Name

I/O

No.

Description

Rn, Gn, Bn,

DE, HSYNC,

VSYNC

I

51

TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control

lines HSYNC, VSYNC, DE (Data Enable).(Note 12)

AnP

O

8

Positive LVDS differential data output.

AnM

O

8

Negative LVDS differential data output.

CLKIN

I

1

TTL level clock input.

R_FB

I

1

Programmable data strobe select. Rising data strobe edge selected when

input is high. (Note 12)

R_FDE

I

1

Programmable control (DE) strobe select. Tied high for data active when DE

is high. (Note 12)

CLK1P

O

1

Positive LVDS differential clock output.

CLK1M

O

1

Negative LVDS differential clock output.

PD

I

1

TTL level input. Assertion (low input) tri-states the outputs, ensuring low

current at power down. (Note 12)

PLLSEL

I

1

PLL range select. This pin must be tied to V

Ground is reserved for future use. Typical shift point is between 55 and 68

MHz. (Notes 12, 14)

BAL

I

1

Mode select for DC Balanced (new) or non-DC Balanced (backward

compatible) interface. DC Balance is active when input is high. NC or tied to

Ground, the DC Balance function is disabled. (Notes 12, 13, 15)

PRE

I

1

Pre-emphasis level select. Pre-emphasis is active when input is tied to V

CC

through external pull-up resistor. Resistor value determines pre-emphasis

level (see table in application section). For normal LVDS drive level (No

pre-emphasis) leave this pin open (do not tie to ground).(Note 12)

DUAL

I

1

Three-mode select for dual pixel, single pixel, or single pixel input to dual

pixel output operation. Single pixel mode when input is low (only LVDS

channels A0 thru A3 and CLK1 are active) for power savings. Dual mode is

active when input is high. Single in - dual out when input is at 1/2 Vcc. (Note

12)Figure 16

V

CC

I

4

Power supply pins for TTL inputs and digital circuitry.

GND

I

5

Ground pins for TTL inputs and digital circuitry.

PLLV

CC

I

2

Power supply pin for PLL circuitry.

PLLGND

I

3

Ground pins for PLL circuitry.

LVDSV

CC

I

3

Power supply pin for LVDS outputs.

LVDSGND

I

4

Ground pins for LVDS outputs.

CLK2P/NC

O

1

Additional positive LVDS differential clock output. Identical to CLK1P. No

connect if not used.

CLK2M/NC

O

1

Additional negative LVDS differential clock output. Identical to CLK1M. No

connect if not used.

Note 12: Inputs default to “low” when left open due to internal pull-down resistor.

Note 13: DC Balancing is functionally tested on Automatic Test Equipment (ATE) at 85 MHz only. A sample of characterization units have been bench tested at 112

MHz to verify full speed performance.

Note 14: The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time.

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