VCM Control Register

Address: 0001

Bit Function

Mnemonic

Bit #

Init State

R/W

Read 1 indicates:

VCM DAC attenuation

switches - 3 bits (5)d

1.5:1

ATT0

0

xxx

W

N/A

2:1

ATT1

1

xxx

W

N/A

4:1

ATT2

2

xxx

W

N/A

Thermal Limit

TH_LIM

3

0

Read

Th Limit

Register Park

RPARK

4

On

R/W

Park Delay is

Occuring (1)

Saturate Seek

SAT_SK

5

0

R/W

Driver Saturated (2)

VCM Tristate

VCM_3S

6

xxx

W

Tristated (3)

VCM loopback (read)

Done Disable (write) (6)

VCM_LP

DONE_DIS

7

7

xxx

Read

Write

Current

Outside

Window (4)

(1) Register park will not cause a brake to occur. The register park bit will also go low during a register brake, indicating to the firmware that

the brake sequence has been initiated.

(2) Saturated seek bit, when 1, will cause the VCM drivers to saturate, with the polarity of the sign bit in the VCM DAC register. A read of this

bit indicates that the commanded current differs from the actual current (output of the saturation comparator). NOTE: this is not just an

echo of the state of the written bit, but actually represents the true status of the VCM current loop.

(3) This bit tristates but leaves internal circuitry active for external test (ST), or is unused (Unitrode). The DONE_DIS bit has been moved

(see note 4).

(4) VCM loopback is optional. Use the saturated seek bit for test purposes. The DONE_DIS bit is used to end the park timer cycle, which

may be necessary if the chip is ever put into run mode at low speed.

(5) Exact attenuation ratios may vary slightly between manufacturers. See data sheets. Attenuators are now gated by ATT_EN, which is lo-

cated in S2 in the address space of the VCM register. IfATT_EN is high, the attenuation is set by the value in this register. If ATT_EN is

low, full gain (no attenuation) is selected. This allows rapid switching between low and high gain with the same write packet as that used

to write to the DAC.

(6) DONE_DIS MUST be cleared when entering run mode, or the park timer will stay off. This bit should never be used except during error

recovery.

Commutation Preload Register (CPR-Write only)

Address: 0011

Bit Function

Bit Address

Spindle ABC low enb (3 bits)

initial state: XXX (2)

A low enb

Bit 0

B low enb

Bit 1

C low enb

Bit 2

Spindle ABC high enb (3 bits)

initial state: XXX (2)

A high enb

Bit 3

B high enb

Bit 4

C high enb

Bit 5

Spare

Bit 6

Spare

Bit 7

NOTES:

- All bits become valid only on a rising SP_CLK edge, except CHB_ENB.

- Spindle high bits override low bits. Transition from low to high and vice versa are interlocked against simultaneous enables or momentary

shootthrough.

- An all 1’s pattern in this register, bits 0 through 5, causes the internal Commutation Counter to begin operation on the next SPIN_CLK input

edge. Any other pattern causes the spindle Commutation Counter to reset (BC\ state).

(1) CHB_ENB, when high (the POR and default condition), allows the back EMF chop blanking comparator to disable spindle PWM off peri-

ods during the A phase negative crossing (see back EMF detection section). Initial state varies between vendors.

(2) the 6 bits which determine the spindle driver must be set to all 1’s before entering run mode or the CCTR will not run.

L6256

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