BLOCK DIAGRAM DESCRIPTION

(see Block Diagram)

Inside the I.C. there are two unipolar stepper mo-

tor drivers, one bridge driver for DC motor, 4x4 bit

latch registers, one shift register. the input logic,

the charge pump, and the thermal protection.

The following conditions are valid for all the 3

driver sections:

1)When the osc/res pin is tied to GND, an inter-

nal reset signal is generated which switches

off all the outputs and resets the internal reg-

isters.

2)The conditions 1 is valid also during power on

and power off transitions.

3)During power on and power off, the I.C. is

puts are switched off.

Input Logic

The input CMOS logic interfaces the microproces-

sor logic to the 4 registers. An integrated Schmitt-

trigger circuit is used to improve noise immunity

at each logic input.

The data is introduced in the 16bit shift register by

the SID pin. The first bit b 15 after 16 clock ap-

plied to SCK pin will be the D15 of the shift regis-

ter.

On the falling edge of STB the 16 bits of the shift

register are transferred to the outputs of the 4

latch registers. Fig 2 shows the timing.

CHA and CHB Stepper Motor Drivers

REGISTER 1

D0

D1

D2

D3

=

=

=

=

PHASE 1A

NPHASE 2A

PHASE 3A

NPHASE 4A

CHANNEL A

CHANNEL A

CHANNEL A

CHANNEL A

REGISTER 2

D0

D1

D2

D3

=

=

=

=

PHASE 1B

NPHASE2B

PHASE 3B

NPHASE4B

CHANNEL B

CHANNEL B

CHANNEL B

CHANNEL B

REGISTER 3

D0

D1

D2

D3

=

=

=

=

D/A CHANNEL A

D/A CHANNEL A

D/A CHANNEL B

D/A CHANNEL B

LEAST

MOST

LEAST

MOST

REGISTER 4

D0

D1

D2

D3

=

=

=

=

INPUT 1

INPUT 2

V2 VOLTAGE

V2 VOLTAGE

CHANNEL C

CHANNEL C

CHANNEL C

CHANNEL C

Registers

The Combo Motor Driver controls the 3 channels using 4 latch registers of 4 bit each:

D0

D1

D2

D3

OUT1 A/B

OUT2 A/B

OUT3 A/B

OUT4 A/B

0

1

1

0

0

0

0

0

1

0

0

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

OFF

ON

ON

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

ON

ON

ON

OFF

OFF

OFF

OFF

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

ON

ON

ALL THE OTHERS

OFF

OFF

OFF

OFF

Register 1/2 Output Status (CHA and CHB) . See note 1

DO

D1

REFER. VOLT AGE CHANNEL A

0

0

1

1

0

1

0

1

0.125 V

0.250 V

0.375 V

0.500 V

Register 3 Current Reference (D/A OUTPUT)

D2

D3

REFER. VOLTAGE CHANNEL B

0

0

1

1

0

1

0

1

0.125 V

0.250 V

0.375 V

0.500 V

L6285

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