W164

Rev 1.0, November 28, 2006

Page 7 of 11

Note:

2. CPU and PCI frequency selections are listed in Table 1 and Table 5.

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

If Spread Is On

Data Byte 3, Bit 3 = 1

CPU, SDRAM

Clocks (MHz)

PCI Clocks

(MHz)

Spread Percentage

Bit 7

SEL_3

Bit 6

SEL_2

Bit 5

SEL_1

Bit 4

SEL_0

0

0

0

0

68.5

34.25

±0.5% Center

0

0

0

1

75

37.5

±0.5% Center

0

0

1

0

83.3

41.6

±0.5% Center

0

0

1

1

66.8

33.4

±0.5% Center

0

1

0

0

103

34.25

±0.5% Center

0

1

0

1

112

37.3

±0.5% Center

0

1

1

0

133.3

33.3

±0.5% Center

0

1

1

1

100

33.3

±0.5% Center

1

0

0

0

117

39.0

±0.5% Center

1

0

0

1

117

29.25

±0.5% Center

1

0

1

0

124

31.0

±0.5% Center

1

0

1

1

129

32.25

±0.5% Center

1

1

0

0

138

34.5

±0.5% Center

1

1

0

1

143

35.75

±0.5% Center

1

1

1

0

148

37.0

±0.5% Center

1

1

1

1

153

38.25

±0.5% Center

Table 6. Select Function for Data Byte 3, Bits 0:1

Function

Input Conditions

Output Conditions

Data Byte 3

CPU0:1

PCI_F, PCI1:6

REF2X,

IOAPIC

48MHZ

24MHZ

Bit 1

Bit 0

Normal Operation

0

0

Note 2

Note 2

14.318 MHz

48 MHz

24 MHz

Test Mode

0

1

X1/2

CPU/2, 3, or 4

X1

X1/2

X1/4

Spread Spectrum

1

0

±0.5%

±0.5%

14.318 MHz

48 MHz

24 MHz

Three-state

1

1

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z