80C286 datasheet(17/60 Pages) INTERSIL

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Protected Virtual Address Mode

The 80C286 executes a fully upward-compatible superset of

the 80C86 instruction set in protected virtual address mode

(protected mode). Protected mode also provides memory

management and protection mechanisms and associated

instructions.

The 80C286 enters protected virtual address mode from real

address mode by setting the PE (Protection Enable) bit of

the machine status word with the Load Machine Status Word

(LMSW) instruction. Protected mode offers extended physi-

cal and virtual memory address space, memory protection

mechanisms, and new operations to support operating sys-

tems and virtual memory.

All registers, instructions, and addressing modes described

in the 80C286 Base Architecture section of this Functional

Description remain the same. Programs for the 80C86,

80C88, and real address mode 80C286 can be run in pro-

tected mode; however, embedded constants for segment

selectors are different.

Memory Size

The protected mode 80C286 provides a 1 gigabyte virtual

address space per task mapped into a 16 megabyte physical

address space defined by the address pins A23-A0 and

BHE. The virtual address space may be larger than the

physical address space since any use of an address that

does not map to a physical memory location will cause a

restartable exception.

Memory Addressing

As in real address mode, protected mode uses 32-bit point-

ers, consisting of 16-bit selector and offset components. The

selector, however, specifies an index into a memory resident

table rather than the upper 16-bits of a real memory address.

The 24-bit base address of the desired segment is obtained

from the tables in memory. The 16-bit offset is added to the

segment base address to form the physical address as

shown in Figure 8. The tables are automatically referenced

by the CPU whenever a segment register is loaded with a

selector. All 80C286 instructions which load a segment reg-

ister will reference the memory based tables without addi-

tional software. The memory based tables contain 8 byte

values called descriptors.

Descriptors

Descriptors define the use of memory. Special types of

descriptors also define new functions for transfer of control

and task switching. The 80C286 has segment descriptors for

code, stack and data segments, and system control descrip-

tors for special system data segments and control transfer

operations. Descriptor accesses are performed as locked

bus operations to assure descriptor integrity in multi-proces-

sor systems.

Code and Data Segment Descriptors (S = 1)

Besides segment base addresses, code and data descriptors

contain other segment attributes including segment size (1 to

64K bytes), access rights (read only, read/write, execute only,

and execute/read), and presence in memory (for virtual mem-

ory systems) (See Table 10). Any segment usage violating a

segment attribute indicated by the segment descriptor will pre-

vent the memory cycle and cause an exception or interrupt.

Code and data (including stack data) are stored in two types

of segments: code segments and data segments. Both types

are identified and defined by segment descriptors (S = 1).

Code segments are identified by the executable (E) bit set to

1 in the descriptor access rights byte. The access rights byte

of both code and data segment descriptor types have three

fields in common: present (P) bit, Descriptor Privilege Level

(DPL), and accessed (A) bit. If P = 0, any attempted use of

this segment will cause a not-present exception. DPL speci-

fies the privilege level of the segment descriptor. DPL con-

trols when the descriptor may be used by a task (refer to

privilege discussion below). The A bit shows whether the

segment has been previously accessed for usage profiling, a

necessity for virtual memory systems. The CPU will always

set this bit when accessing the descriptor.

PHYSICAL

ADDRESS

ADDER

MEMORY

OPERAND

SEGMENT

DESCRIPTOR

SEGMENT BASE

ADDRESS

POINTER SELECTOR OFFSET

PHYSICAL MEMORY

SEGMENT

16 15

CPU

FIGURE 8. PROTECTED MODE MEMORY ADDRESSING

RESERVED †

ACCESS

RIGHTS BYTE

PDPL STYPE A

BASE 23 - 16

BASE 15 - 0

LIMIT 15 - 0

70 7

†

MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES

FIGURE 9. CODE OR DATA SEGMENT DESCRIPTOR

80C286

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