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DS36C280TM Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DS36C280TM Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 9 page  DS36C280 Slew Rate Controlled CMOS EIA-RS-485 Transceiver General Description The DS36C280 is a low power differential bus/line trans- ceiver designed to meet the requirements of RS-485 Stan- dard for multipoint data transmission. In addition, it is com- patible with TIA/EIA-422-B. The slew rate control feature allows the user to set the driver rise and fall times by using an external resistor. Controlled edge rates can reduce switching EMI. The CMOS design offers significant power savings over its bipolar and ALS counterparts without sacrificing ruggedness against ESD damage. The device is ideal for use in battery powered or power conscious applications. I CC is specified at 500 µA maximum. The driver and receiver outputs feature TRI-STATE® capa- bility. The driver outputs operate over the entire common mode range of −7V to +12V. Bus contention or fault situa- tions are handled by a thermal shutdown circuit, which forces the driver outputs into the high impedance state. The receiver incorporates a fail safe circuit which guarantees a high output state when the inputs are left open (Note 1) . Features n 100% RS-485 compliant — Guaranteed RS-485 device interoperation n Low power CMOS design: I CC 500 µA max n Adjustable slew rate control — Minimizes EMI affects n Built-in power up/down glitch-free circuitry — Permits live transceiver insertion/displacement n SOIC packages n Industrial temperature range: −40˚C to +85˚C n On-board thermal shutdown circuitry — Prevents damage to the device in the event of excessive power dissipation n Wide common mode range: −7V to +12V n Receiver open input fail-safe (Note 1) n 1 ⁄4 unit load (DS36C280): ≥128 nodes n 1 ⁄2 unit load (DS36C280T): ≥64 nodes n ESD (human body model): ≥2kV Connection and Logic Diagram 01205201 Order Number DS36C280M, DS36C280TM See NS Package Number M08A Truth Table DRIVER SECTION DE/RE* DI DO/RI DO*/RI* HH H L HL L H LX Z Z RECEIVER SECTION DE/RE* RI-RI* RO L ≥+0.2V H L ≤−0.2V L HX Z L OPEN (Note 1) H Note 1: Non-terminated, Open Inputs only TRI-STATE® is a registered trademark of National Semiconductor Corporation. July 2000 © 2004 National Semiconductor Corporation DS012052 www.national.com |
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