CAT9555

12

Doc. No. MD-9003 , Rev. G

© Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Figure 10. Read from Register

Figure 11. Read Input Port Register

Power-On Reset Operation

When the power supply is applied to VCC pin, an internal

power-on reset pulse holds the CAT9555 in a reset state

condition is released and the internal state machine and

the CAT9555 registers are initialized to their default

state.

S

A

1

0

A2

A1 A0

0

0

0

0

A2

A1

A0

0

1

A

A

COMMAND BYTE

acknowledge

from slave

acknowledge

from slave

A

P

NA

acknowledge

from slave

acknowledge

from master

S

DATA

DATA

R/W

first byte

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

last byte

no acknowledge

from master

1

slave address

data from upper

or lower byte of

register

data from lower

or upper byte

of register

slave address

MSB

LSB

MSB

LSB

0

NOTE: Transfer can be stopped at any time by a STOP condition.

R/W

12345

6789

S

0100

A2

A1

A0

1

A

A

I0.x

A

I1.x

A

I0.x

1

I1.x

P

R/W

ACKNOWLEDGE

FROM SLAVE

SCL

SDA

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

DATA 00

DATA 10

DATA 03

DATA 12

DATA 00

DATA 01

DATA 02

DATA 03

DATA 10

DATA 11

DATA 12

NOTE:

Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port register).