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L6996

conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the ref-

erence voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the induc-

tor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV

and 2V to ensure the system linearity.

1.2 Closing the loop

The loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator

negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes

lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side

MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the pre-

vious section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side

MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way.

For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the aver-

age output voltage is different from the programmed one as shown in figure 13.

Figure 13. Valley Regulation

Figure 14. Voltage positioning network

The L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5m

Ω

sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure

14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current

Time

Vout

Vref

<Vout>

DC Error Offset

R4

R1

L6996

Vprog

R3

R2

To Vout

Rsense

To inductor

-

+

VFB-

VFB+

COMPARATOR

PWM