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L9230 Datasheet(PDF) 10 Page - STMicroelectronics |
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L9230 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 25 page  L9230 10/25 t v Data Valid CL = 40pF Data Valid CL = 200pF (referred to L9230) 40 150 ns ns t su Data Setup Time (referred to master) 50 ns t h Data Hold Time (referred to master) 20 ns t dis Disable Time (referred to L9230) 100 ns t dt Transfer Delay (referred to master) 150 ns t SCKH Serial clock high time (referred to master) 50 µs t SCKL Access time (referred to master) 8.35 ns Clock inactive before chipselect becomes valid 200 ns Clock inactive after chipselect becomes valid 200 ns t rs rise-, fall time Load on SO 50pF 20 ns DIAGNOSTIC Diagnostic Threshold (Open Load Detection DMS > 4,5V, EN < 0,8V) VOUT1 VOUT2 Load is available 0.8 0.8 V V VOUT1 VOUT2 Load is missing 1 VS 0.8 V V IOUT2 -IOUT1 Diagnostic Current DMS > 4.5V, EN < 0.8V DMS > 4.5V, EN < 0.8V 700 1000 1000 1500 1300 2000 µA µA Tracking Diagnostic Current IOUT1 / IOUT2 1.4 1.5 1.6 tD Delay Time 30 100 ms Symbol Parameter Test Condition Min. Typ. Max. Unit |
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