F320C3BD datasheet(22/68 Pages) INTEL

22 / 68 page

Intel£ Advanced+ Boot Block Flash Memory (C3)

Datasheet

The 12 V VPP mode enhances programming performance during the short period of time typically

found in manufacturing processes; however, it is not intended for extended use. 12 V may be

applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main

blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80

hours maximum. Stressing the device beyond these limits may cause permanent damage.

4.2.2

Suspending and Resuming Program

The Program Suspend command halts an in-progress program operation so that data can be read

from other locations of memory. Once the programming process starts, issuing the Program

Suspend command to the CUI requests that the WSM suspend the program sequence at

predetermined points in the program algorithm. The device continues to output status-register data

after the Program Suspend command is issued. Polling status-register bits SR[7] and SR[2] will

determine when the program operation has been suspended (both will be set to “1”). tWHRH1/

tEHRH1 specify the program-suspend latency.

A Read-Array command can now be issued to the CUI to read data from blocks other than that

which is suspended. The only other valid commands while program is suspended are Read Status

After the Program Resume command is issued to the flash memory, the WSM will continue with

the programming process and status register bits SR[2] and SR[7] will automatically be cleared.

The device automatically outputs status register data when read (see Figure 14, “Program Suspend

/ ResumeFlowchart”on page53) after the Program Resume command is issued. VPP must remain

at thesameVPP level used for program while in program-suspend mode. RP# must also remain at

VIH.

4.3

Erase Mode

To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an

address identifying the block to be erased. This address is latched internally when the Erase

Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only

one block can be erased at a time. The WSM will execute a sequence of internally timed events to

program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all

bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

When the status register indicates that erasure is complete, check the erase-status bit to verify that

the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the status

the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,

SR[5] of the status register is set to indicate an erase error, and SR[3] is set to a “1” to identify that

VPP supply voltage was not within acceptable limits.

After an Erase operation, clear the status register (0x50) before attempting the next operation. Any

CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-

F320C3BD Datasheet(PDF) 22 Page - Intel Corporation