High-drive Two-Channel LVDS Repeater/Mux
ComLink™ Series
CY2LL843
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07066 Rev. OBS
Revised December 02, 2004
Features
• ANSI TIA/EIA-644-1995-compliant
• Designed for data rates to > 700 Mbs = (350 MHz)
• Single 2 × 2 with high-drive output drivers
• Low -voltage differential signaling with output voltages
of ± 350 mV into 50-ohm load version (Bus LVDS)
• Single 3.3V supply
• Accepts ± 350-mV differential inputs
• Output Drivers are high-impedance when disabled or
when VDD ≤1.5V
• 16-pin SOIC/TSSOP packages
• Industrial version available
Description
The Cypress CY2LL843 are differential line drivers and
receivers that utilize Low Voltage Signaling or LVDS, to
achieve signaling rates of 700Mbs. The receiver outputs can
be switched to either or both drivers through the multiplexer
control signals S0/S1. This provides flexibility in application for
either a splitter or router configuration with a single device.
The Cypress CY2LL843 are configured as a single
two-channel repeater/Mux.
The LVDS standard provides a minimum differential output
voltage of 247 mV into a 50-ohm load and receipt of as little as
100 mV signals with up to 1V of DC offset between transmitter
and receiver. The Cypress CY2LL843 doubles the output drive
current to achieve BusLVDS signaling levels with a faster
rise/fall times into 50-ohm load.
A doubly terminated BusLVDS line enables multipoint config-
urations.
Designed for both point to point based-band multi-point data
transmission over controlled impedance lines.
Block Diagram
Pin Configuration
1Y
1Z
2Y
2Z
VDD
1A
1B
2A
2B
GND
1DE
2DE
S0 S1
16 pin SOIC/TSSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
1Y
1Z
2DE
2Z
2Y
GND
1B
1A
S0
1DE
S1
2A
2B
GND
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