1Kx4 Static RAM
CY7C150
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05024 Rev. *A
Revised January 18, 2003
50
Features
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed com-
puters
• CMOS for optimum speed/power
• High speed
— 10 ns (commercial)
— 12 ns (military)
• Low power
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
• 5-volt power supply
±10% tolerance in both commercial
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0 through A9).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0 through O3).
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
C150–1
64 x 64
ARRA
Y
A0
A1
A2
A3
A4
COLUMNDECODER
DATAINPUT
CONTROL
O0
O1
O2
O3
A6 A7 A8
D0 D1 D2 D3
COLUMN
DECODER
OE
WE
CS
RS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
19
22
21
20
Top View
DIP/SOIC
7C150
A3
A4
A5
A6
A7
O2
VCC
A2
WE
CS
OE
O3
D2
D3
C150-2
A8
A9
D0
O0
D1
23
24
A1
A0
RS
O1
GND
A5
A9
Selection Guide
7C150
−10
7C150
−12
7C150
−15
7C150
−25
7C150
−35
Maximum Access Time (ns)
Commercial
10
12
15
25
Military
12
15
25
35
Maximum Operating Current (mA)
Commercial
90
90
90
90
90
Military
100
100
100
100
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