AM79C961 datasheet(39/173 Pages) AMD

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Am79C961

Plug and Play Logical Device Control Registers

Activate

0x30

For each logical device there is one activate register that controls whether or not

the logical device is active on the ISA bus. Bit[0], if set, activates the logical device.

Bits[7:1] are reserved and must be zero. This is a read/write register. Before a

logical device is activated, I/O range check must be disabled.

I/O Range Check

0x31

This register is used to perform a conflict check on the I/O port range programmed

for use by a logical device.

Bit[7:2] Reserved

Bit 1[1] Enable I/O Range check, if set then I/O Range Check is enabled. I/O range

check is only valid when the logical device is inactive.

Bit[0], if set, forces the logical device to respond to I/O reads of the logical device’s

assigned I/O range with a 0x55 when I/O range check is in operation. If clear, the

logical device drives 0xAA. This register is read/write.

Name

Address

Port Value

Definition

Memory Space Configuration

Memory base address

0x40

Read/write value indicating the selected memory base address bits[23:16] for

bits[23:16] descriptor 0

memory descriptor 0. This is the Boot Prom Space.

Memory base address

0x41

Read/write value indicating the selected memory base address bits[15:08] for

bits[15:08] descriptor 0

memory descriptor 0.

Memory control

0x42

Bits[2:1] specifies 8/16-bit control. The encoding is identical to memory control

(bits[4:3]) of the information field in the memory descriptor.

Bit[0], =0, indicates the next field is used as a range length for decode

(implies range length and base alignment of memory descriptor are equal).

Bit[0] is read-only.

Memory upper limit

0x43

Read/write value indicating the selected memory high address bits[23:16] for

address;

memory descriptor 0.

If bit[0] of memory control is 0, this is the range length.

If bit[0] of memory control is 1, this is considered invalid.

Memory upper limit

0x44

Read/write value indicating the selected memory high address bits[15:08] for

memory descriptor 0, either a memory address or a range length as described above.

Memory descriptor 1

0x48-0x4C

Memory descriptor 1. This is the SRAM Space for Shared Memory.

Name

Index

Definition

bits[23:16] or range

length;

bits[23:16] for

descriptor 0

bits[15:08] or range

length;

bits[15:08] for

descriptor 0

I/O Space Configuration

I/O port base address

0x60

Read/write value indicating the selected I/O lower limit address bits[15:08] for I/O

bits[15:08] descriptor 0

descriptor 0. If a logical device indicates it only uses 10 bit encoding, then bits[15:10]

do not need to be supported.

I/O port base address

0x61

Read/write value indicating the selected I/O lower limit address bits[07:00] for I/O

bits[07:00] descriptor 0

descriptor 0.

Name

Index

Definition

AM79C961 Datasheet(PDF) 39 Page - Advanced Micro Devices

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