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CY29774
Document #: 38-07479 Rev. **
Page 3 of 9
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 33.3 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 25 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 16.6 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 12.5 MHz
÷48
Input Clock * 48
4.2 MHz to 10.4 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
Default
0
1
TCLK_SEL
0
TCLK0
TCLK1
VCO_SEL
0
VCO
÷2 (high input frequency range)
VCO
÷4 (low input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
Outputs enabled
CLK_STP#
1
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
SELB
QB(4:0)
SELC
QC(3:0)
00
÷40
÷40
÷8
01
÷81
÷81
÷12
10
÷80
÷80
÷16
11
÷16
1
÷16
1
÷24
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
000
÷8
001
÷16
010
÷12
011
÷24
100
÷16
101
÷32
110
÷24
111
÷48
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