AD9960

Rev. 0 | Page 4 of 12

SPECIFICATIONS

ANALOG SPECIFICATIONS

TMIN to TMAX, unless otherwise specified; analog and digital supplies = 3.3 V ± 10%; fCLKIN = 32 MHz. TxDAC settings: fDAC = 32 MSPS;

8× interpolation; IOUTFS = 20 mA1; differential load resistance of 25 Ω2; unless otherwise noted. RxADC settings: fADC = 64 MSPS3 ;

no decimation, internal VREF; differential 3 V p-p analog inputs; unless otherwise noted.

Table 1. Tx Path Specifications

Parameter

Min

Typ

Max

Unit

Tx PATH GENERAL

Resolution

12

Bits

Maximum DAC Update Rate

32

MHz

Maximum Full-Scale Output Current

2

20

mA

Gain Mismatch Error

−2

+2

% FS

Offset Mismatch Error

−2

+2

% FS

Voltage Reference (REFIO)

1.23

V

Output Voltage Compliance Range

–1.0

+1.3

V

Tx PATH DYNAMIC PERFORMANCE

(IOUTFS = 20 mA; fOUT = 100 kHz)

SNR

71

73

dBFS

SINAD

70

dB

THD

–79

–71

dBc

SFDR, Wideband (DC to Nyquist)

83

dBc

Table 2. Rx Path Specifications

Parameter

Min

Typ

Max

Unit

Rx PATH GENERAL

Resolution

14

Bits

Maximum I/Q Channel Sample Rate

32

MSPS

Reference Voltage (VREF)

1.44

1.5

1.55

V

Differential Analog Input Voltage Range

2

3

V p-p

Gain Error (with Internal VREF)

2

2

% FS

Gain Drift (with Internal VREF)

±25

ppm/C

Gain Mismatch Error

±0.1

% FS

Offset Mismatch Error

±0.3

% FS

Aperture Uncertainty (Jitter)

1

ps rms

Input-Referred Noise

150

μV rms

Rx PATH DYNAMIC PERFORMANCE

(VIN = −0.5 dBFS; fIN = 1 MHz)

SNR

71

74

dBc

SINAD

70

72

dBc

THD (2nd to 9th Harmonic)

−79

−71

dBc

SFDR, Wideband (DC to Nyquist)

74

82

dBc

1 RSET = 1.31 kΩ with internal VREF DAC.

2 Results in 1 V p-p maximum differential voltage with common-mode voltage set to 0.5 V to replicate dc-coupled input to quadrature modulator.

3 2× clock multiplier enabled.