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UC1697V Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers

Part # UC1697V
Description  128 x 128RGB C-STN LCD Controller-Driver w/ 16-bit per RGB On-Chip SRAM
PDF  77 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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UC1697V Datasheet(HTML) 21 Page - List of Unclassifed Manufacturers

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UC1697v
128x128RGB CSTN Controller-Driver
Revision A_0.6
17
(12) SET PARTIAL DISPLAY CONTROL
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
Set Partial Display Enable LC [9:8]
0
0
100001
LC9 LC8
This command is used to enable partial display function.
LC[9:8] : 0xb: Disable Partial Display, Mux-Rate = CEN+1 (DST, DEN not used.)
10b: Enable Partial Display, Mux-Rate = CEN+1
11b: Enable Partial Display, Mux-Rate = DEN-DST+1+ LC[0]x(FLT+FLB)x2
(13) SET RAM ADDRESS CONTROL
Action
C/D W/R D7
D6
D5
D4
D3
D2
D1
D0
Set AC [2:0]
0
0
10001
AC2 AC1 AC0
Program registers AC[2:0] for RAM address control.
AC[0]: WA, Automatic column/row wrap around.
0: CA or RA (depends on AC[1]= 0 or 1) will stop incrementing after reaching boundary
1
: CA or RA (depends on AC[1]= 0 or 1) will restart, and RA or CA will increment by one step.
AC[1]: Auto-Increment order
0
: column (CA) increment (+1) first until CA reaches CA boundary, then RA will increment by (+/-1).
1 : row (RA) increment (+/-1) first until RA reach RA boundary, then CA will increment by (+1).
AC[2]: RID, row address (RA) auto increment direction ( 0/1 = +/- 1 )
When WA=1 and CA reaches CA boundary, RID controls whether row address will be adjusted by
+1 or -1.
AC[2:0] controls the auto-increment behavior of CA and RA. For Window Program enabling (AC[3]=ON), see
section Command Description (34) ~ (37) for more details. If WPC[1:0] and WPP[1:0] values are the default
values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[3] is.



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