TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Functional Description
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an
external device to TP6312 through the serial interface,
and is assigned addresses as follows, in units of 8
bits:
Seg1
Seg4
Seg8
Seg12
Seg16
00HL
00HU
01HL
01HU
DIG1
02HL
02HU
03HL
03HU
DIG2
04HL
04HU
05HL
05HU
DIG3
06HL
06HU
07HL
07HU
DIG4
08HL
08HU
09HL
09HU
DIG5
0AHL
0AHU
0BHL
0BHU
DIG6
0CHL
0CHU
0DHL
0DHU
DIG7
0EHL
0EHU
0FHL
0FHU
DIG8
10HL
10HU
11HL
11HU
DIG9
12HL
12HU
13HL
13HU
DIG10
14HL
14HU
15HL
15HU
DIG11
b0
b3 b4
b7
XX HL
XX HU
Lower 4 bits
Higher 4 bits.
Key Matrix and Key-Input Data Storage
RAM
The Key matrix is of 6
× 4 configuration, as shown
below.
KEY1
KEY2
KEY3
KEY4
The data of each Key is stored as illustrated below,
and is read by a read command, starting from the
least significant bit.
Key1
Key4 Key1
Key4
Seg1 / KS1
Seg2 / KS2
Seg3 / KS3
Seg4 / KS4
Seg5 / KS5
Seg6 / KS6
Reading sequence
b0
b3 b4
b7
LED Port
Data is written to the LED port by a write command,
starting from the least significant bit of the port.
When a bit of this port is 0, the corresponding LED
lights; when the bit is 1, the LED goes off.
The data
of bits 5 through 8 is ignored.
----
----
----
----
b3
b2
b1
b0
Don't care
LED1
LED2
LED3
LED4
On power application, all LEDs are unlit.
SW Data
The SW data is read by a read command, starting
from the least significant bit.
Bits 5 through 8 of the
SW data are 0.
0
0
0
0
b3
b2
b1
b0
SW1
SW2
SW3
SW4
MSB
LSB
Commands
A command sets the display mode and status of the
VFD driver.
The first 1 byte input to TP6312 through the DIN pin
after the STB pin has fallen is regarded as a
command.
If STB is high while a command/data is transmitted,
serial
communication
is
initialized,
and
the
transmitting command/data is invalid; however, the
Version 1.1
Page 3 of 9
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September 2003
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