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M14256, M14128

Figure 5. Write Mode Sequences with WC=1

BYTE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01120B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

ACK

NO ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

NO ACK

Write Operations

Following a START condition the master sends a

Device Select code with the RW bit set to ’0’, as

shown in Table 6. The memory acknowledges it

and waits for two bytes of address, which provides

access to the memory area. After receipt of each

byte address, the memory again responds with an

acknowledge and waits for the data byte. Writing

in the memory may be inhibited if the input pin WC

is taken high.

Any write command with WC=1 (during a period of

time from the START condition until the end of the

two bytes address) will not modify the memory

content and will NOT be acknowledged on data

bytes, as shown in Figure 5.

Byte Write

In the Byte Write mode, after the Device Select

code and the address, the master sends one data

byte. If the addressed location is write protected by

the WC pin, the memory replies with a NoACK,

and the location is not modified. If, instead, the WC

pin has been held at 0, as shown in Figure 6, the

memory replies with an ACK. The master termi-

nates the transfer by generating a STOP condi-

tion.

Page Write

The Page Write mode allows up to 64 bytes to be

written in a single write cycle, provided that they

are all located in the same ’row’ in the memory:

that is the most significant memory address bits

(b14-b6 for the M14256 and b13-b6 for the

M14128) are the same. The master sends from

one up to 64 bytes of data, each of which is ac-

knowledged by the memory if the WC pin is low. If

the WC pin is high, each data byte is followed by a

NoACK and the location is not modified. After each

byte is transferred, the internal byte address coun-

ter (the six least significant bits only) is increment-

ed. The transfer is terminated by the master

generating a STOP condition. Care must be taken

to avoid address counter ’roll-over’ which could re-

sult in data being overwritten. Note that, for any