M24256, M24128

10/17

Table 10. AC Characteristics

Note: 1. For a reSTART condition, or following a write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Symbol

Alt.

Parameter

M24256 / M24128

Unit

MinMax

MinMax

Clock Rise Time

300

300

ns

Clock Fall Time

300

300

ns

SDA Rise Time

20

300

20

300

ns

SDA Fall Time

20

300

20

300

ns

Clock High to Input Transition

600

600

ns

Clock Pulse Width High

600

600

ns

Input Low to Clock Low (START)

600

600

ns

Clock Low to Input Transition

0

0

µs

Clock Pulse Width Low

1.3

1.3

µs

Input Transition to Clock Transition

100

100

ns

Clock High to Input High (STOP)

600

600

ns

Input High to Input Low (Bus Free)

1.3

1.3

µs

Clock Low to Data Out Valid

200

900

200

900

ns

Data Out Hold Time After Clock Low

200

200

ns

Clock Frequency

400

400

kHz

Write Time

10

10

ms

cremented. The master terminates the transfer

with a STOP condition, as shown in Figure 8,

with-

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master

this case, and the memory continues to output the

next byte in sequence. To terminate the stream of

bytes, the master must

byte output, and

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’

and the memory continues to output data from

memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its stand-by state.