| Electronic Components Datasheet Search |
|
SMC032AF Datasheet(PDF) 15 Page - Numonyx B.V |
|
|
|||||||||||||||||||||||||||||
SMC032AF Datasheet(HTML) 15 Page - Numonyx B.V |
|
15 / 82 page ![]() SMCxxxAF Electrical interface 15/82 20 A00 I I1Z A00 I I1Z A00 I I1Z 21 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 D00 I/O I1Z,OZ3 22 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 D01 I/O I1Z,OZ3 23 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 D02 I/O I1Z,OZ3 24 WP O OT3 –IOIS16 O OT3 –IOIS16 O ON3 25 –CD2 O Ground –CD2 O Ground –CD2 O Ground 26 –CD1 O Ground –CD1 O Ground –CD1 O Ground 27 D11(2) I/O I1Z,OZ3 D11(2) I/O I1Z,OZ3 D11(2) I/O I1Z,OZ3 28 D12(2) I/O I1Z,OZ3 D12(2) I/O I1Z,OZ3 D12(2) I/O I1Z,OZ3 29 D13(2) I/O I1Z,OZ3 D13(2) I/O I1Z,OZ3 D13(2) I/O I1Z,OZ3 30 D14(2) I/O I1Z,OZ3 D14(2) I/O I1Z,OZ3 D14(2) I/O I1Z,OZ3 31 D15(2) I/O I1Z,OZ3 D15(2) I/O I1Z,OZ3 D15(2) I/O I1Z,OZ3 32 –CE2(2) II3U –CE2(2) II3U –CS1(2) II3Z 33 –VS1 O Ground –VS1 O Ground –VS1 O Ground 34 –IORD I I3U –IORD I I3U –IORD I I3Z 35 –IOWR I I3U –IOWR I I3U –IOWR I I3Z 36 –WE I I3U –WE I I3U –WE(3) II3U 37 READY O OT1 IREQ O OT1 INTRQ O OZ1 38 VCC Power VCC Power VCC Power 39 –CSEL(2)(4) II2Z –CSEL I I2Z –CSEL I I2U 40 –VS2 O OPEN –VS2 O OPEN –VS2 O OPEN 41 RESET I I2Z RESET I I2Z -RESET I I2Z 42 –WAIT O OT1 –WAIT O OT1 IORDY O ON1 43 –INPACK O OT1 –INPACK O OT1 RFU O OZ1 44 –REG I I3U –REG I I3U RFU(5) II3U 45 BVD2 I/O I1U,OT1 –SPKR I/O I1U,OT1 –DASP I/O I1U,ON1 46 BVD1 I/O I1U,OT1 –STSCHG I/O I1U,OT1 –PDIAG I/O I1U,ON1 47 D08(2) I/O I1Z,OZ3 D08(2) I/O I1Z,OZ3 D08(2) I/O I1Z,OZ3 48 D09(2) I/O I1Z,OZ3 D09(2) I/O I1Z,OZ3 D09(2) I/O I1Z,OZ3 49 D10(2) I/O I1Z,OZ3 D10(2) I/O I1Z,OZ3 D10(2) I/O I1Z,OZ3 50 GND Ground GND Ground GND Ground 1. The signal should be grounded by the host. 2. These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current. 3. The signal should be tied to VCC by the host. 4. The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card in these modes it should not be left floating by the host in PC Card modes. In these modes, the pin is normally connected by the host to PC Card A25 or grounded by the host. 5. The signal should be held High or tied to VCC by the host and RFU is Reserved for Future Use. Table 8. Pin assignment and pin type (continued) Pin num PC card memory mode PC card I/O mode True IDE mode Signal name Pin type In, Out type Signal name Pin type In, Out type Signal name Pin type In, Out type |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |