MPC8309CVMADDC datasheet(29/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Ethernet and MII Management

8.3.4

IEEE 1588 AC Specifications

The IEEE 1588 AC timing specifications are given in the following table.

Input high voltage

VIH

—

2.0

OVDD + 0.3

Input low voltage

VIL

—

- 0.3

0.8

Input current

IIN

0V ≤ VIN ≤ OVDD

—± 5

μA

Table 27. IEEE 1588 AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 300mV.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

QE_1588_CLK clock period

tT1588CLK

2.5

—

TRX_CLK  9ns

1, 3

QE_1588_CLK duty cycle

tT1588CLKH/tT1588CLK

—

QE_1588_CLK peak-to-peak jitter

tT1588CLKINJ

——

250

—

Rise time QE_1588_CLK

(20%–80%)

tT1588CLKINR

1.0

—

2.0

—

Fall time QE_1588_CLK

(80%–20%)

tT1588CLKINF

1.0

—

2.0

—

QE_1588_CLK_OUT clock period

tT1588CLKOUT

 tT1588CLK

——

—

QE_1588_CLK_OUT duty cycle

tT1588CLKOTH

/tT1588CLKOUT

—

QE_1588_PULSE_OUT

tT1588OV

0.5

—

3.0

—

QE_1588_TRIG_IN pulse width

tT1588TRIGH

 tT1588CLK_MAX

——

Notes:

1.TRX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8309

PowerQUICC II Pro Integrated Communications Processor Reference Manual,

for a description of TMR_CTRL registers.

2. It needs to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8309 PowerQUICC

II Pro Integrated Communications Processor Reference Manual,

for a description of TMR_CTRL registers.

3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For

example, for 10/100 Mbps modes, the maximum value of tT1588CLK is 3600 and 280ns, respectively.

Table 26. IEEE 1588 DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

unit

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