MPC8309CVMADFC datasheet(9/81 Pages) NXP

9 / 81 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Electrical Characteristics

2.1.2

Power Supply Voltage Specification

The following table provides the recommended operating conditions for the MPC8309. Note that these

values are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8309

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD

Table 2. Recommended Operating Conditions

Characteristic

Symbol

Recommended

Value

Unit

Note

Core supply voltage

VDD

1.0 V ± 50 mV

PLL supply voltage

AVDD1

AVDD2

AVDD3

1.0 V ± 50 mV

DDR2 DRAM I/O voltage

GVDD

1.8 V ± 100 mV

PCI, Local bus, DUART, system control and power management,

I2C, SPI, MII, RMII, MII management, eSDHC, FlexCAN,USB and

JTAG I/O voltage

OVDD

3.3 V ± 300 mV

1, 3

Junction temperature

TA/TJ

0to105

C2

Notes:

1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative

direction.

2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction

Temperature).

3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/OVDD + 20%

G/OVDD

G/OVDD + 5%

of tinterface1

1. tinterface refers to the clock period associated with the bus clock interface.

VIH

VIL

Note:

MPC8309CVMADFC Datasheet(PDF) 9 Page - NXP Semiconductors

MPC8309CVMADFC Datasheet(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL