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TMS320DM643 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM643 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 162 page  www.ti.com 1 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor 1.1 Features TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007 Memory Space • High-Performance Digital Media Processor • Enhanced Direct-Memory-Access (EDMA) – 2-, 1.67-ns Instruction Cycle Time Controller (64 Independent Channels) – 500-, 600-MHz Clock Rate – Eight 32-Bit Instructions/Cycle • 10/100 Mb/s Ethernet MAC (EMAC) – 4000, 4800 MIPS – IEEE 802.3 Compliant – Fully Software-Compatible With C64x™ – Media Independent Interface (MII) – 8 Independent Transmit (TX) Channels and • VelociTI.2™ Extensions to VelociTI™ 1 Receive (RX) Channel Advanced Very-Long-Instruction-Word (VLIW) • Management Data Input/Output (MDIO) TMS320C64x™ DSP Core – Eight Highly Independent Functional Units • Two Configurable Video Ports (VP1, VP2) With VelociTI.2™ Extensions: – Providing a Glueless I/F to Common Video • Six ALUs (32-/40-Bit), Each Supports Decoder and Encoder Devices Single 32-Bit, Dual 16-Bit, or Quad 8-Bit – Supports Multiple Resolutions/Video Stds Arithmetic per Clock Cycle • VCXO Interpolated Control Port (VIC) • Two Multipliers Support Four 16 x 16-Bit – Supports Audio/Video Synchronization Multiplies (32-Bit Results) per Clock • Host-Port Interface (HPI) [32-/16-Bit] Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle • Multichannel Audio Serial Port (McASP) – Load-Store Architecture With Non-Aligned – Eight Serial Data Pins Support – Wide Variety of I2S and Similar Bit Stream – 64 32-Bit General-Purpose Registers Format – Instruction Packing Reduces Code Size – Integrated Digital Audio I/F Transmitter – All Instructions Conditional Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats • Instruction Set Features • Inter-Integrated Circuit (I2C Bus™) – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection • Multichannel Buffered Serial Port – Bit-Field Extract, Set, Clear – CLKS Input Not Supported – Normalization, Saturation, Bit-Counting • Three 32-Bit General-Purpose Timers – VelociTI.2™ Increased Orthogonality • Sixteen General-Purpose I/O (GPIO) Pins • L1/L2 Memory Architecture • Flexible PLL Clock Generator – 128K-Bit (16K-Byte) L1P Program Cache • IEEE-1149.1 (JTAG) Boundary- (Direct Mapped) Scan-Compatible – 128K-Bit (16K-Byte) L1D Data Cache (2-Way • 548-Pin Ball Grid Array (BGA) Package Set-Associative) (GDK and ZDK Suffixes), 0.8-mm Ball Pitch – 2M-Bit (256K-Byte) L2 Unified Mapped • 548-Pin Ball Grid Array (BGA) Package RAM/Cache (Flexible RAM/Cache Allocation) (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch • Endianess: Little Endian, Big Endian • 0.13-µm/6-Level Cu Metal Process (CMOS) • 64-Bit External Memory Interface (EMIF) • 3.3-V I/O, 1.2-V Internal (-500) – Glueless Interface to Asynchronous • 3.3-V I/O, 1.4-V Internal (-600) Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) – 1024M-Byte Total Addressable External Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Windows is a registered trademark of Microsoft Corporation. I2C Bus is a trademark of Philips Electronics N.V. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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