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ST7LITEU05 Datasheet(PDF) 49 Page - STMicroelectronics |
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ST7LITEU05 Datasheet(HTML) 49 Page - STMicroelectronics |
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49 / 115 page  ST7LITEU05 ST7LITEU09 49/115 Figure 32. I/O Port General Block Diagram Table 15. I/O Port Mode Options Legend:NI - not implemented Off - implemented not activated On - implemented and activated DR DDR OR PAD VDD ALTERNATE ENABLE ALTERNATE OUTPUT 1 0 OR SEL DDR SEL DR SEL PULL-UP CONDITION P-BUFFER (see table below) N-BUFFER PULL-UP (see table below) 1 0 ANALOG INPUT If implemented ALTERNATE INPUT VDD DIODES (see table below) FROM OTHER BITS EXTERNAL SOURCE (eix) INTERRUPT POLARITY SELECTION CMOS SCHMITT TRIGGER REGISTER ACCESS Configuration Mode Pull-Up P-Buffer Diodes to VDD to VSS Input Floating with/without Interrupt Off Off On On Pull-up with/without Interrupt On Output Push-pull Off On Open Drain (logic level) Off 1 |
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