 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST7LITEU09 Datasheet(PDF) 36 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7LITEU09 Datasheet(HTML) 36 Page - STMicroelectronics |
|
|
36 / 115 page  ST7LITEU05 ST7LITEU09 36/115 SYSTEM INTEGRITY MANAGEMENT (Cont’d) Figure 21. Using the AVD to Monitor VDD 8.4.3 Low Power Modes 8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). VDD VIT+(AVD) VIT-(AVD) AVDF bit 01 RESET IF AVDIE bit = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT Cleared by VIT+(LVD) VIT-(LVD) LVD RESET Early Warning Interrupt (Power has dropped, MCU not not yet in reset) 0 1 hardware INTERRUPT Cleared by reset Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
