LR38617

4

PIN NO. SYMBOL IO SYMBOL POLARITY

PIN NAME

DESCRIPTION

20

–

Power supply

Supply of +3.3 V power.

An input pin for resetting all internal circuits at power-on.

the capacitor.

All clear input

ICU3

ACLX

21

–

A grounding pin.

Ground

–

GND

23

22

RS

O6MA3

S/H pulse output

A pulse to sample-hold the signal for the CDS circuit.

The output phase and output polarity of RS are selected

by serial data.

24

TIN

IC3

Test input

A test pin. Set to L level in normal mode.

–

–

A pulse to clamp the optical black signal.

This pulse is controlled by serial data BCPCNT.

BCPCNT = H; This pulse stays high during the

absence of effective pixels within the

vertical blanking or during the

sweepout signal.

BCPCNT = L; This pulse stays high during sweepout

signal.

Optical black clamp

pulse output

O3

BCPX

14

–

–

An input pin for reference clock oscillation.

The frequency is 36.00 MHz.

Clock input

OSCI3

CKI

25

26

CKO

OSCO3

Clock output

An output pin for reference clock oscillation.

The output is the inverse of CKI (pin 25).

–

An output pin to generate HD and VD pulses.

The frequency is 18.00 MHz.

Clock output

O6MA3

CLK

27

28

DCLK

O6MA3

Clock output

An output pin for DSP IC. The frequency is 18.00 MHz.

The output phase of DCLK is selected by serial data in

90˚ steps.

An input pin for reference of vertical pulse.

Connect to VD pin of DSP IC.

Vertical reference

pulse input

IC3

VD

29

30

–

Power supply

Supply of +3.3 V power.

–

–

A grounding pin.

Ground

–

GND

31

19

FS

O6MA3

CDS pulse output 2

A pulse to sample-hold the signal for the CCD.

The output phase and output polarity of FS are selected

by serial data.

15

CLPX

O3

Clamp pulse output

A pulse to clamp the dummy outputs of the CCD signal.

This pulse stays high during the sweepout period.

16

ADCK

O6MA3

AD clock output

An output pin for AD converter. The output phase of

ADCK is selected by serial data in 90˚ steps.

17

GND

–

Ground

–

A grounding pin.

18

FCDS

O6MA3

CDS pulse output 1

A pulse to clamp the feed-through level for the CCD.

The output phase and output polarity of FCDS are

selected by serial data.